1. Field of the Invention
The present invention relates to an integrated device with a Built-in Self Testing (BIST) circuit for executing a structured test.
2. Description of the Related Art
The structured test is a technique that has become increasingly popular in the last years, especially for testing complex integrated circuits. For this purpose, the integrated device is provided with internal structures permitting the controllability and the observability of each pin and/or internal sequential element (referred to as a node).
A known and commonly used technique for executing the structured test is the scan method. In this method, the integrated device is provided with boundary scan cells (for the pins) and/or internal scan cells (for the internal nodes). The boundary scan cells are serially connected in a chain and the internal scan cells are serially connected in one or more chains (between corresponding input pins and output pins of the integrated device). Input patterns (commonly referred to as input test vectors) are serially loaded along the chains of scan cells for exciting the pins and the internal nodes of the integrated device. The values generated in response to the input test vectors (commonly referred to as output test vectors) are captured by the corresponding scan cells and then provided to the outside by shifting them along the chains. The output test vectors can then be compared with expected test data, representing the correct known output test vectors. The above-described architecture makes it possible to execute the structured test with a very low impact on the integrated device.
In a different architecture, disclosed in document U.S. Pat. No. 5,872,793, the integrated device is provided with a pseudo-random pattern generator for supplying the input test vectors in response to starting test vectors (commonly referred to as seeds), which are received from the outside.
The main disadvantage of the solutions known in the art is the use of external test equipment for applying the input test vectors or the seeds to the integrated device and for comparing the output test vectors with the expected test data. Furthermore, it is necessary to carefully synchronize the external test equipment with a system clock of the integrated device for detecting transition faults in the functional circuitry; therefore, when the frequency of operation of the integrated device is high, the external test equipment becomes very expensive.
BIST circuits for executing the structured test have also been proposed. The BIST circuit is essentially the implementation of logic built into the integrated device to do testing. The BIST circuit is triggered by an external signal, and it returns a value indicating the passing or the failing of the test. This structure allows testing the integrated device both before and after assembly into a complex system (such as a computer). In the BIST circuits known in the art for executing the structured test, the input test vectors are generated inside the integrated device from a hardwired starting value. However, this structure provides poor performance in terms of fault coverage.
The possibility to implement a reliable and fast BIST circuit for executing the structured test on the integrated devices would be desirable. Particularly, this need is perceived when the integrated devices must be assembled in safety systems (such as AIRBAGs and ABSs in automotive devices), which need to be tested during all their life time without the use of external test equipments.